非易失内存和DRAM — Nonvolatile Memory and DRAM.pdf
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ISSCC 2025
SESSION 30
Nonvolatile Memory
and DRAM
30.1 A 28Gb/mm
2
4XX-Layer 1Tb 3b/cell WF-Bonding 3D-NAND Flash with 5.6Gb/s/pin IOs
© 2025 IEEE
International Solid-State Circuits Conference
1 of 24
A 28Gb/mm2 4XX-Layer 1Tb 3b/cell WF-
Bonding 3D-NAND Flash with 5.6Gb/s/pin
IOs
Sang-Soo Park, Jae-Doeg Lyu, Myungjun Kim, Jaeyun Lee, Younsun Song, Chung-Ho Yu, Hirano Makoto, Yongseok
Kwon, Jong-Hoon Park, Ho-Joon Kim, Daein Lee, Donghyun Seo, Byungrok Go, Seoyoon Jeon, Yoonjee Kim, Doo-
Hyun Kim, Youngmin Jo, Hyunjun Yoon, Junehong Park, Inmo Kim, Sunghoon Kim, Hokil Lee, Je-Hyeon Yu, Sang-
Lok Kim, Hwan-Seok Ku, Jungmin Seo, Jindo Byun, Seung-Hyeon Yun, Kyoungtae Kang, Seung-Beom Kim, Yohan
Lee, Yongkyu Lee, Kyunghwa Kang, Han-Jun Lee, Younghwan Ryu, Hyundo Kim , Wontae Kim, Hyeongdo Choi,
Juho Jeon, Ansoo Park, Raehyun Song, Jae-Hwan Kim, Jung-Soo Kim, Hwa-Seok Lee, Moo-Kyung Lee, Jae-Ick Son,
Jiho Cho, Moosung Kim, Jae-Woo Im, Jongmin Park, Hyuckjoon Kwon, Youngdon Choi, Chiweon Yoon, Seungjae
Lee, Kiwhan Song, Sung-Hoi Hur
Samsung Electronics, Hwaseong, Korea
30.1 A 28Gb/mm
2
4XX-Layer 1Tb 3b/cell WF-Bonding 3D-NAND Flash with 5.6Gb/s/pin IOs
© 2025 IEEE
International Solid-State Circuits Conference
2 of 24
Outline
Introduction
NAND Challenges
Merits of BV-NAND Architecture(IO, Bit-density)
Key Features
Key Design
2-Transistor Coded-GSL
Stack-Dependent Pass-Voltage Control
External Power Assisted Core Driving
Proposed SCA protocol with /ODT
Low power High speed IO scheme for 5.6-Gb/s/pin (PI-LTT, DFE, RDCA)
Conclusion
of 159
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